View MD1812K6-G_1278178.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Supertex inc.
High Speed Quad MOSFET Driver
Features
6ns rise and fall time 2A peak output source/sink current 1.2V to 5V input CMOS compatible 5V to 12V supply voltage operation Smart Logic threshold Low jitter design Quad matched channels Drives two N and two P-channel MOSFETs Outputs can swing below ground Built-in level translator for negative gate bias User-defined damping for return-to-zero application Low inductance quad flat no-lead package Thermally-enhanced package
MD1812
Initial Release
General Description
The Supertex MD1812 is a high-speed quad MOSFET driver. It is designed to drive two N and two P-channel high voltage DMOS FETs for medical ultrasound applications but may be used in any application that needs a high output current for a capacitive load. The input stage of the MD1812 is a high-speed level translator that is able to operate from logic input signals of 1.2 to 5.0 volt amplitude. An adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic 1 levels. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1812 has separate power connections enabling the output signal L and H levels to be chosen independently from the driver supply voltages. As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and -5V, and the output L and H levels may be varied anywhere over the range of -5V to +5V. The output stage is capable of peak currents of up to 2 amps, depending on the supply voltages used and load capacitance. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly pre-charging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A builtin level shifter provides P-MOS gate negative bias drive. This enables the user-defined damping control to generate return-to-zero bipolar output pulses.
Applications
Ultrasound PN code transmitter Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation High speed level translator High voltage bipolar pulser
Typical Application Circuit
+100V +10V 0.22 F 14 16 OE 15 1 INA INB LT 5 INC VDD 11 VH OUTA 13 OUTB 12 OUTG 10 2K OUTC OUTD GND 3 VSS 7 2 VL VNEG 4 -10V 9 8 10nF 10nF -100V 10nF +10V 1F 0.47 F
3.3V CMOS Logic Inputs
Supertex TC6320
1F
6
IND
0.47 F
Supertex MD1812 Supertex TC2320
NR031706
Supertex inc.
* 1235 Bordeaux Drive, Sunnyvale, CA 94089 * Tel: (408) 222-8888 * FAX: (408) 222-4895 * www.supertex.com
1
MD1812
Package Option Device 16-lead 4x4x0.9 QFN MD1812
-G indicates package is RoHS compliant (`Green')
MD1812K6-G
16-Lead QFN (K6) Package
16-Lead QFN (K6) Pin Configuration
16 13
1
12
MD1812
4 9
5
8
Top View
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function INB VL GND VNEG INC IND VSS OUTD OUTC OUTG VH OUTB OUTA VDD INA OE Description Logic input. Controls OUTB when OE is high.. Supply voltage for N-channel output stage. Device ground. Supply voltage the auxiliary gate drive. Logic input. Controls OUTC when OE is high. Logic input. Controls OUTD when OE is high. Supply voltage for low-side analog, level shifter, and gate drive circuit. Output driver. Output driver. Auxiliary output driver. Supply voltage for P-channel output stage Output driver. Output driver. Supply voltage for high-side analog, level shifter, and gate drive circuit. Logic input. Controls OUTA when OE is high. Output enable logic input.
Note: Thermal pad and pin #4, VNEG must be connected externally.
NR031706
2
MD1812
Absolute Maximum Ratings
Parameter VDD-VSS, Logic Supply Voltage VH, Output High Supply Voltage VL, Output Low Supply Voltage Vss, Low Side Supply Voltage VNEG-VSS, Negative Supply Voltage Logic Input Levels Maximum Junction Temperature Storage Temperature Soldering Temperature Package Power Dissipation Value -0.5V to +13.5V VL-0.5V to VDD+0.5V VSS-0.5V to VH+0.5V -7V to +0.5V VSS-13.5V to VSS+0.5V VSS-0.5V to VSS+7V +125C -65C to 150C 235C 2.2W
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
DC Electrical Characteristics
(VH = VDD = 12V, VL = VSS = GND = 0V, VNEG = -12V, VOE = 3.3V, TJ = 25OC)
Symbol
VDD - VSS VSS VH VL VNEG IDDQ IHQ INEGQ IDD IH INEG VIH VIL IIH IIL VIH VIL RIN CIN
Parameter
Logic supply voltage Low side supply voltage Output high supply voltage Output low supply voltage Negative supply voltage VDD quiescent current VH quiescent current VNEG quiescent current VDD average current VH average current VNEG average current Input logic voltage high Input logic voltage low Input logic current high Input logic current low OE Input logic voltage high OE Input logic voltage low Input logic impedance to GND Logic input capacitance
Min
4.5 -5.5 VSS+2 VSS -13 VOE-0.3 0 1.2 0 12 -
Typ
1.5 7.0 22 1.5 20 5
Max
13 0 VDD VDD-2 VSS-2 10 10 5 0.3 1.0 1.0 5 0.3 30 10
Units
V V V V V mA A A mA mA mA V V A A V V K pF
Conditions
--------May connect to VSS if OUTG not used
No input transitions, OE = 1
One channel on at 5.0Mhz, No load
For logic inputs INA, INB, INC, and IND
For logic input OE
---
NR031706
3
MD1812
Outputs
(VH = VDD = 12V, VL = VSS = GND = 0V, VNEG = -12V, VOE = 3.3V, TJ = 25OC)
Symbol RSINK RSOURCE ISINK ISOURCE
Parameter Output sink resistance Output source resistance Peak output sink current Peak output source current
Min -
Typ 2.0 2.0
Max 12.5 12.5 -
Units A A
Conditions ISINK = 50mA ISOURCE = 50mA -----
AC Electrical Characteristics
(VH = VDD = 12V, VL = VSS = GND = 0V, VNEG = -12V, VOE = 3.3V, TJ = 25OC)
Symbol tirf tPLH tPHL tPOE tPCG tr tf l tr - tf l l tPLH-tPHL l tdm
Parameter Input or OE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low Propagation delay OE to output Propagation delay INC to OUTG Output rise time Output fall time Rise and fall time matching Propagation low to high and high to low matching Propagation delay matching
Min -
Typ 7 7 9 28 6 6 1.0 1.0 2.0
Max 10 -
Units ns ns ns ns ns ns ns ns ns ns
Conditions Logic input edge speed requirement
CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2ns
for each channel Device to device delay match
Logic Truth Table
Logic Inputs OE H H H H L OE H H H H L INA L L H H X INC L L H H X INB L H L H X IND L H L H X OUTC VH VH VL VL VH OUTA VH VH VL VL VH OUTG VSS VSS VNEG VNEG VSS Output OUTB VH VL VH VL VL OUTD VH VL VH VL VL
NR031706
4
MD1812
Application Information
For proper operation of the MD1812, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB, INC, IND and OE pins should be connected to a logic source with a swing of GND to VCC, where VCC is 1.2 to 5.0 volts. When input logic(s) is high, output(s) will swing to VL, and when input(s) logic is low, output(s) will swing to VH. All inputs must be kept low until the device is powered up. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1812 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane, with short leads and decoupling components to prevent resonance in the power leads. Output drivers, OUTA and OUTC, drive the gate of an external Pchannel MOSFET, while output drivers OUTB and OUTD drive the gate of an external N-channel MOSFET, and they all swing from VH to VL. The auxiliary output drive, OUTG, swings from VSS to VNEG, and drives the gate of an external P-channel MOSFET via a 2K series resistor. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1.0F may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area, and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will reduce the output voltage slew rate at the terminals of a capacitive load. The OE pin sets the threshold level of logic for inputs (VOE + VGND) / 2. When OE is low, OUTA and OUTC are at VH. OUTB and OUTD are at VL. Auxiliary output OUTG, is at VSS, regardless of the inputs INA or INB. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V, even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. Best timing performance is obtained for OUTC when the voltage of (VSSVNEG) = (VH-VL).
NR031706
5
MD1812
16-Lead QFN Package Outline (K6)
D D/2 INDEX AREA (D/2 xE/2) 4 -B-
-A -
Datum A or B 4 l1
1
E/2
e
Chamfer/Radius
E
aaa C 2x
Terminal Tip 5
e/2
4
N
N-1
aaa C 2x TOP VIEW ccc C NX 0.08 C SIDE VIEW
Symbol
Height Dimensions Min N om 4.0 4.0 0.65 2.0 2.0 0.25 0.45 0.80 0.00 --0.03 A 2.15 2.15 0.30 0.55 0.90 0.02 0.20 ref --2.25 2.25 0.35 0.65 1.0 0.05 --0.15 Max
Tolerance of Form & Position aaa bbb ccc ddd Issue 0.15 0.10 0.10 0.05 A
D B SC
SEATING PLANE -C-
E B SC e D2
A A1
D2 D2/2
A3
E2 b l
NXl
E2/2
A
E2
-B-
e
A1 A3
1
L1
N N-1 NXb
Issue
CA B
INDEX AREA (D/2 xE/2) 4 SEE DETAIL B
-A-
bbb C ddd
Bottom ID Dimensions AA .344 BB .344 CC .181 DD .181
BTM VIEW
Notes: 1. Dimensioning and tolerancing conform to ASME Y14.5m - 1994. 2. All dimensions are in millimeters, all angles are in degrees (O). 3. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95, SPP-002. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1identifier may be either a mold or marked feature. 4. Depending on the method of lead termination at the edge of the package, pull back (L1) may be present. L minus L1 to be equal to or greater than 0.33mm. 5. Dimension B applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension B should not be measured in that radius area.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in such applications, unless it receives an adequate "product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http//www.supertex.com.
(c)2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 / FAX: (408) 222-4895
Doc.# DSFP - MD1812 NR031706
www.supertex.com
6

▲Up To Search▲

Price & Availability of MD1812K6-G

	To Download MD1812K6-G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .